This invention relates to an improvement of a semiconductor switching device with anode shorting structure and particularly, to a gate turn-off thyristor (GTO) with anode shorting structure which has an enhanced gate trigger sensitivity and a reduced turn-off loss.
A gate turn-off thyristor or GTO can be turned off by applying a negative voltage to the gate electrode thereof to draw part of the anode current from the gate electrode. Time required for turning off the GTO, or the gate turn-off time, is a very important characteristic because it determines the upper limit of the operation frequency of an equipment utilizing the GTO. The gate turn-off time becomes long with increase in the diameter and thickness of a silicon wafer used to form a GTO of large electric power capacity.
In order to solve the above problem, a GTO of anode shorting structure is proposed, which has part of an n-type base layer formed in direct contact with the anode electrode (which is disclosed in, for example, Japanese Patent Publication No. 55-10143). FIGS. 33(a), (b) and (c) shows the construction of the GTO. FIG. 33(a) is a plan view of the GTO as viewed from the cathode side thereof, and FIGS. 33(b) and (c) are cross-sectional views of the GTO OF FIG. 33(a) taken along lines A--A' and B--B', respectively. The GTO has a pnpn structure comprising p.sup.+ -type emitter layers (first emitter layer) 51, n.sup.- -type base layer (first base layer) 52, p-type base layer (second base layer) 53 and n.sup.+ -type emitter layers (second emitter layer) 54 which are separately formed in long and narrow patterns. Anode electrode (first main electrode) 56, cathode electrodes (second main electrode) 55 and gate electrode 57 are respectively formed on the surfaces of p.sup.+ -type emitter layers 51, n.sup.+ -type layers 54 and an p-type base layer 53.
Those portions of n.sup.- -type base layer 52 which correspond in position to the cathode electrodes extend to anode electrode 56 to make a flat surface with p.sup.+ -type emitter layers 51 and contact with anode electrode 56. The extending portions are used as shorting portions 58. Formation of shorting portions 58 makes it possible to effectively drive out carriers n.sup.- -type base layer 52 via anode electrode 56 at the turn-off time, thereby reducing the turn-off time.
FIGS. 34(a), (b) and (c) show an example in which n.sup.+ -type buffer layer 59 with low resistivity is additionally formed to reduce the thickness of the GTO shown in FIGS. 33(a) to (c). This example is introduced in Japanese Patent Disclosure No. 56-6790. FIG. 34(a) is a plan view of the GTO as viewed from the cathode side thereof, and FIGS. 34(b) and (c) are cross-sectional views of the GTO of FIG. 34(a) taken along lines A--A' and B--B', respectively. Formation of n.sup.+ -type buffer layer 59 with low resistivity permits the thickness of n.sup.- -type base layer 52 of high resistivity to be reduced, attaining a low turn-on voltage. The combination of n.sup.+ -type buffer layer 59 with low resistivity and the anode shorting structure can further improve the turn-off characteristic.
However, the GTO with the anode shorting structure including the n.sup.+ -type buffer layer as shown in FIGS. 34(a) to (c) has a problem that the gate trigger sensitivity is lowered. The problem is caused by the fact that resistance Rs of a shorting resistor connected between the base and emitter of a parasitic pnp transistor formed of the p-type emitter, n-type base and p-type base, as is shown in an equivalent circuit of FIG. 34(d), becomes too small due to the presence of n.sup.+ -type buffer layer 59 with low resistivity.
In the GTO shown in FIGS. 33(a) to (c) or FIGS. 34(a) to (c), p-type base layer 53 and p.sup.+ -type emitter layer 51 are simultaneously formed in the same impurity diffusion step to have the diffusion depth xj of, for example, 70 to 90 .mu.m. The reason is as follows. The depth of n.sup.+ -type emitter layer 54 is an important factor to determine the characteristics of the GTO and it is necessary to form p-type base layer 53 and p.sup.+ -type emitter layer 51 to a certain diffusion depth in order to set the diffusion depth of n.sup.+ -type emitter layer 54. The reason why p.sup.+ -type emitter layer 51 is formed thick is that, in the prior art, a Mo layer or W layer is alloyed as a heat buffering plate with a silicon pellet. In this case, the alloy layer is formed as thick as 20 to 30 .mu.m, at the time of formation of the alloy layer, a spike of aluminum electrode (56) may happen to be projected into the silicon pellet as deep as 60 .mu.m. For this reason, it is desirable to form p.sup.+ -type emitter layer 51 to a thickness of 70 to 90 .mu.m.
In the case where p.sup.+ -type emitter layer 51 is formed thick in the GTO shown in FIGS. 33(a) to (c), impurities are diffused in lateral directions when shorting portions 58 are formed by diffusion, making it impossible to reduce the size of shorting portions 58.
In the case where p.sup.+ -type emitter layer 51 is formed thick in the GTO having n.sup.+ -type buffer layer 59 of low resistivity as shown in FIGS. 34(a) to (c), it is practically impossible to form n.sup.+ -type buffer layer 59 by diffusion. Therefore, in this case, it is necessary to n.sup.+ -type buffer layer 59 by epitaxial growth technique. At this time, if defects are created in the step of epitaxial growth, the withstanding or breakdown voltage is lowered, resulting in lowering the yield.
As described above, in the GTO of the anode shorting structure having the n.sup.+ -type buffer layer, the gate turn-off time can be made shorter as the anode shorting rate is made larger, reducing the reactive power consumed at the turn-off time or the turn-off time loss. However, in this case, the trigger sensitivity will be lowered.
Anode shorting rate ASR is defined by the following equation: EQU ASR=S1/S2.times.100 (%)
where S1 is a contact area of the anode electrode (56) and the shorting portion (58), and S2 is a projection area of the emitter layer (54) projected onto the anode electrode (56).